MicroFPGA

THE COMING REVOLUTION IN SMALL ELECTRONICS

# MICROFPGA These are the slides for a [talk](https://youtu.be/ME_e06ApxJA) given at the Superconference 2019 Use arrow keys to transistion from slide to slide. A weird gray rectangle on the RHS of a slide means that it can be explored with mouse clicks A version of the slides with more material is available [here](https://davidthings.github.io/spokefpga/hackaday_slides_2019_11_12/index_full.html#/) The slides are built with [reveal.js](https://revealjs.com). The zooming slides are created using [Sozi](https://sozi.baierouge.fr/). Module diagrams are built using [HDElk](https://davidthings.github.io/hdelk/). Other diagrams are drawn with [Inkscape](https://inkscape.org/).

# WALKER <img class="img-75" src="images/start/quad_robot.png"></img>

# 3D PRINTING AND RAW MATERIALS <img class="img-75" src="images/start/ExampleUniversalFrame.png"></img>

# MODULAR JOINTS <img class="img-50" src="images/start/big_tube_core_render.png"></img>

# WITH BIG FAT STEPPERS <img class="img-50" src="images/start/big_tube_nut_holes.png"></img>

# NETWORKS OF SENSORS AND ACTUATORS <img class="img-75" src="images/intro/robot_architecture.svg"></img>

# BUT <img class="img-25" src="images/intro/robo_sad.svg"></img> <p class="fragment">Communications too slow</p> <p class="fragment">Not enough GPIO at microcontrollers</p> <p class="fragment">FPGA-curious?!</p>

# AREN'T FPGAS EXPENSIVE & INTIMIDATING? <img class="img-33" src="images/fpgas/vcu129-angled.jpg"></img> <img class="img-33" src="images/fpgas/vivado_block.png"></img>

# NEW BOARD OPTIONS **NEW!** Smaller boards, for smaller applications <img class="img-25" src="images/fpgas/TinyFPGA_BX_Board-01.jpg"></img> <img class="img-25" src="images/fpgas/fomu-front-back-03_png_project-body.jpg"></img> <img class="img-25" src="images/fpgas/icebreaker-iso.jpg"></img> <p class="fragment" >TinyFPGA BX $45, Fomu $45, iCEBreaker $65</p>

# OPEN SOURCE TOOLS **NEW!** Fast open source tools and libraries <img class="img-50 " src="images/fpgas/nextpnr-ice40.png"></img> <!-- <img class="img-33" src="images/fpgas/next-pnr-closeup.png"></img> --> <p class="fragment" >eg. Yosys, NextPnR, IceStudio, Migen </p>

What Is An FPGA?

# DISCRETE LOGIC <img class="img-50" src="images/intro/NV_0417_Julstrom_Figure03.jpg"></img> <p class="mini">https://www.nutsvolts.com/magazine/article/April2017_CMOS-ICs-Digital-Clock</p> MC4543 - BCD-to-Seven Segment Latch/Decoder/Driver

NATIONAL SEMICONDUCTOR SC/MP

Photo by Pauli Rautakorpi - Own work, CC BY 3.0, Link

Simple Cost-effective Micro Processor. 1974. 1MHz - 4MHz

# STM32 "BLUE PILL" <img class="img-75" src="images/mcus/stm32_pinout.png"></img>

FPGA

https://www.flickr.com/photos/htomari/22054207552/

FIELD PROGRAMMABLE GATE ARRAY

# HARDWARE DESCRIPTION LANGUAGE <img class="img-50" src="images/fpgas/fpga_verilog.svg"></img> ### VERILOG

# REGISTER TRANSFER LANGUAGE <img class="img-75" src="images/fpgas/fpga_rtl.svg"></img>

# HARDWARE <img class="img-75" src="images/fpgas/fpga_physical.svg"></img>

# TOOLS <img class="img-75" src="images/fpgas/fpga_tools.svg"></img> Open Source Tools <img class="img-75" src="images/coding/symbiflow.svg"></img>

# MODULE ``` verilog module add_accum( clock, reset, x, valid, accumsum ); input clock, reset; input [3:0] x; input valid; output reg [7:0] accumsum; always @(posedge clock) begin if ( reset ) accumsum <= 0; else if ( valid ) accumsum <= accumsum + x; end endmodule ``` After RESET, on each CLOCK tick, if VALID, add X to ACCSUM

# YOSYS - PARSE <img class="img-75" src="images/fpgas/add_accum_parse_00.svg"></img>

# YOSYS - PROC <img class="img-75" src="images/fpgas/add_accum_proc_01.svg"></img>

# YOSYS - CLEAN <img class="img-75" src="images/fpgas/add_accum_clean_02.svg"></img>

# YOSYS - ALUMACC <img class="img-75" src="images/fpgas/add_accum_alumacc_03.svg"></img> Strap in...

# YOSYS - TM ARITH <img class="img-33" src="images/fpgas/add_accum_tm_arith_04.svg"></img>

# YOSYS - ABC <img class="img-50" src="images/fpgas/add_accum_abc_05.svg"></img>

# YOSYS - CLEAN <img class="img-33" src="images/fpgas/add_accum_clean_06.svg"></img>

# YOSYS - FFINIT <img class="img-33" src="images/fpgas/add_accum_ffinit_08.svg"></img>

# YOSYS - CLEAN <img class="img-33" src="images/fpgas/add_accum_opt_clean_09.svg"></img>

# YOSYS ABC <img class="img-50" src="images/fpgas/add_accum_abc_10.svg"></img>

# YOSYS - ABC LUT <img class="img-50" src="images/fpgas/add_accum_abc_lut_11.svg"></img>

# YOSYS - CLEAN <img class="img-50" src="images/fpgas/add_accum_clean_12.svg"></img>

# YOSYS - TM CELLS <img class="img-33" src="images/fpgas/add_accum_tm_cells_13.svg"></img>

# YOSYS - CLEAN - FINAL <img class="img-33" src="images/fpgas/add_accum_clean_14.svg"></img>

# PLACE AND ROUTE <img class="img-75" src="images/fpgas/fpga_physical.svg"></img> Now we know *what* is going on the FPGA, *where* should it go?

# PROCESSOR <img class="img-50" src="images/fpgas/fpga_badge.svg"></img> SoftCPU - SoC

# SOFT CPU CODE ``` picorv32 core1 ( .clk (clk ), .resetn (resetn ), .mem_valid (mem_valid ), .mem_instr (mem_instr ), .mem_ready (mem_ready ), .mem_addr (mem_addr ), .mem_wdata (mem_wdata ), .mem_wstrb (mem_wstrb ), .mem_rdata (mem_rdata ) ); ```

# SOFT CPU ARCHITECTURE <img class="img-50" src="images/coding/soc.svg"></img>

# SOFT CPU TOOLCHAIN <img class="img-75" src="images/coding/soc_symbiflow_highlight.svg"></img>

# SOFT CPU APPLICATION ``` C int main() { while (1) { LED = 0xFF; print("hello world\n"); delay(); LED = 0x00; delay(); } } ```

THE BADGE

OUTSIDE

INSIDE

MicroFPGA

# FPGA <img class="img-50" src="images/intro/robot_architecture.svg"></img> ## What changes?

# MICROCONTROLLERS - OUT <img class="img-50" src="images/mcus/stm32_pinout.png"></img> <p class="fragment">Fixed peripherals. Fixed IO's. Slow. One thing at a time.</p>

# FPGAS - IN <img class="img-10" src="images/fpgas/fpga_bg381.jpeg"></img> <img class="img-10" src="images/fpgas/fpga_bga256.jpg"></img> <p class="fragment" >Can have a CPU - can still write code</p> <p class="fragment" >Plenty of IO</p> <p class="fragment" >Fast</p> <p class="fragment" >Write the peripherals you want</p> <p class="fragment" >Upgrade in the Field (it's in the name!)</p>

# USE FPGA MODULES! <img class="img-10" src="images/fpgas/Cmod_A7.png"></img> <img class="img-10" src="images/fpgas/tinyfpga_bx.jpg"></img> <img class="img-10" src="images/fpgas/tiny_fpga_ax2.jpg"></img> <img class="img-10" src="images/fpgas/TEI0003-02_0_600x600.jpg"></img> CMod A7 ($75), TinyFPGA BX ($42), TinyFPGA AX2 ($22), CYC100 ($35) <p class="fragment">No need to work with BGAs directly</p> <p class="fragment">Often Provide: Memory (Flash and RAM), Programming Interface</p>

# WHAT TO DO WITH OLD STANDARDS? <p class="fragment">Often provided as Microcontroller Peripherals</p> <p class="fragment bold"><b>ABANDON STANDARDS YOU DON'T LIKE!</b></p> <p class="fragment bold"><b>WRITE YOUR OWN PERIPHERALS!</b></p>

# USE PMODS! <img class="img-10" src="images/pmods/Pmod_ACL2.png"></img> <img class="img-10" src="images/pmods/Pmod_DPG1.png"></img> <img class="img-10" src="images/pmods/Pmod-ESP32.png"></img> <img class="img-10" src="images/pmods/Pmod_MFG_410-077.jpg"></img> <img class="img-10" src="images/pmods/Pmod_MFG_410-347.jpg"></img> <img class="img-10" src="images/pmods/Pmod_MIC3.png"></img> <img class="img-10" src="images/pmods/Pmod_NAV.png"></img> <img class="img-10" src="images/pmods/Pmod_OLEDrgb.png"></img> <img class="img-10" src="images/pmods/Pmod_RTCC.png"></img> <img class="img-10" src="images/pmods/PmodSSR.png"></img> <img class="img-10" src="images/pmods/EVAL-AD7980-PMDZ.jpg"></img> <img class="img-10" src="images/pmods/EVAL-CN0355-PMDZ.jpg"></img> <img class="img-10" src="images/pmods/DPP401Z000.jpeg"></img> <img class="img-10" src="images/pmods/TEP0002-02.jpg"></img> <img class="img-10" src="images/pmods/TDGL012.jpg"></img> <img class="img-10" src="images/pmods/pmod-hdmi_1024x1024.jpg"></img> <img class="img-10" src="images/pmods/pmod-led-panel_1024x1024.jpg"></img>

# HOW TO CONNECT FPGA MODULES AND PMODS? <img class="img-25" src="images/pmods/Pmod_TinyFPGA_BX_Base_ortho.jpg"></img> Baseboards! <p class="fragment">Easy to design</p> <p class="fragment">Cheap to manufacture</p> <p class="fragment">Present the FPGA IO's in different configurations</p>

# HARDWARE SUMMARY FPGA MODULES - BASE BOARDS - PMODS

# FPGA MODULE <img class="img-50" src="images/fpgas/microfpga_module.svg"></img> Existing or make your own. Share!

# BASE BOARD <img class="img-50" src="images/fpgas/microfpga_base.svg"></img> Existing or make your own. Share!

# PMODS <img class="img-50" src="images/fpgas/microfpga_boards.svg"></img> Existing or make your own. Share!

# HOW TO DO FAST COMMUNICATIONS IN A NOISY ENVIRONMENT <img class="img-25" src="images/pmods/Pmod_MLVDS_ortho.jpeg"></img> M-LVDS *Trivial* at 50Mbps - Goes way up Can add more wires for rate multiplier

# TRANS-SPECIES LOOPBACK <img class="img-50" src="images/pmods/usb_lvds_loopback_hw.jpeg"></img>

# 30 FEET = 60 NS <img class="img-50" src="images/pmods/m-lvds-100Mhz-30ft.jpeg"></img>

# HOW TO DO ANALOG IO? <img class="img-50" src="images/pmods/Pmod_AD5592.jpeg"></img> Put ADC's on the Baseboard or PMods. <p class="fragment">Chips like AD5592R</p>

# HOW TO DO MOTOR CONTROL? <img class="img-50" src="images/pmods/pmod_motor_4_10a_v0_11_kicad_3d.png"></img> <p class="fragment">Motor Drivers</p> <p class="fragment">ADC for voltage and current sensing</p> <p class="fragment">Provision for shaft encoder or resistive position sensor</p> <p class="fragment">All sensing and control through 8 pins</p>

# CODING <img class="img-50" src="images/fpgas/microfpga_code_setup.svg"></img> What about MicroFPGA Coding?

# SoC <img class="img-50" src="images/fpgas/microfpga_soc.svg"></img> <img class="img-33" src="images/coding/soc_symbiflow_highlight.svg"></img>

# VERILOG <img class="img-50" src="images/fpgas/microfpga_verilog.svg"></img> <img class="img-33" src="images/coding/symbiflow.svg"></img>

# MODULARITY Verilog is very low level The temptation to write non-standard interfaces is high! <img class="img-33" src="images/coding/apples.svg"></img> <img class="img-33" src="images/coding/oranges.svg"></img>

# PIPELINES <img class="img-33" src="images/coding/pipelines_data.svg"></img> Industry convention

# DATA <img class="img-33" src="images/coding/pipelines_data.svg"></img> <img class="fragment img-75" src="images/coding/pipelines_data_wave.svg"></img>

# VALID <img class="img-33" src="images/coding/pipelines_data_valid.svg"></img> <img class="fragment img-75" src="images/coding/pipelines_data_valid_wave.svg"></img>

# READY <img class="img-33" src="images/coding/pipelines_data_valid_ready.svg"></img> <img class="fragment img-75" src="images/coding/pipelines_data_valid_ready_wave.svg"></img>

# START / STOP <img class="img-33" src="images/coding/pipelines_data_valid_ready_start_stop.svg"></img> <img class="fragment img-75" src="images/coding/pipelines_data_valid_ready_start_stop_wave.svg"></img>

# PIPES <img class="img-33" src="images/coding/pipelines_data_valid_ready_start_stop.svg"></img> <img class="fragment img-33" src="images/coding/pipelines_pipes.svg"></img> <img class="fragment img-75" src="images/coding/pipelines_p_d8s.svg"></img>

# PIPES ``` verilog producer #( ... ) p ( ... .out_pipe( xferPipe ) ... ); consumer #( ... ) c ( ... .in_pipe( xferPipe ) ... ); ```

# BADGE CAMERA <img class="img-50" src="images/badge/arducam.jpeg"></img> LCD driver and Camera Driver

# IMAGE PIPELINE <img class="img-75" src="images/coding/badge_image_pipeline.svg"></img> <img class="fragment img-75" src="images/coding/pipelines_data_valid_ready_start_stop_wave.svg"></img>

# FIRST FULL FRAME BUILD <img class="img-50" src="images/badge/fpga_cam_full_frame.jpeg"></img>

# CARTRIDGE BOARD <img class="img-50" src="images/badge/spokefpga_camera_cartridge.png"></img>

# WORK IN PROGRESS <p class="fragment">ImageScaler</p> <p class="fragment">BayerToRGB</p> <p class="fragment">Fonts</p> <p class="fragment">Charts</p> <p class="fragment">Multiplexors</p>

WRINKLES

# FPGA DEVELOPMENT IS HARD <p class="fragment">Verilog is not like learning another programming language</p> <p class="fragment">Expect to have to reorganize your brain!</p> <p class="fragment">I got this! I don't got this... (repeat)</p> <p class="fragment">Developing in a strange environment</p> <p class="fragment">Tools are occasionally buggy and frequently obtuse</p> <p class="fragment">Missing FPGA Features</p>

# STATE OF LIBRARIES <p class="fragment">SHOCKING</p> <p class="fragment">Almost 50 years of FPGA development has left miniscule code library trace</p> <p class="fragment">Code is frequently buggy</p> <p class="fragment">Code is frequently unfinished / unmaintained</p> <p class="fragment">Testing is rudimentary</p> <p class="fragment">Do not expect that what you are looking for will be there</p>

# MicroFPGA <p class="fragment em">Design minimalistic FPGA Core Modules!</p> <p class="fragment em">Design diverse base boards!</p> <p class="fragment em">Design Pmod peripherals!</p> <p class="fragment em">Write Modular, Interconnecting FPGA Code!</p> <p class="fragment em">Write libraries for SoftCPU!</p> <p class="fragment em">Develop control and interface technologies!</p> <p class="fragment em">Replace special purpose chips!</p> <p class="fragment em">Stop using annoying standards, replace!</p> <p class="fragment em">Make projects and products with upgradable hardware!</p> <p class="fragment em">Share your stuff! We have 50 years to make up for!</p>

# END ## david@davidthings.com ## @davidthings ## https://github.com/davidthings/spokefpga

NEXT STEPS

# PROJECT IDEAS <p class="fragment">Computational Camera</p> <p class="fragment">Oscilloscope</p> <p class="fragment">Logic Analyser</p> <p class="fragment">Machine Vision</p> <p class="fragment">Machine Hearing</p> <p class="fragment">Machine Touch</p> <p class="fragment">Smart Motor Controller</p> <p class="fragment">Software Defined Radio</p> <p class="fragment">Game Emulation</p>

# FPGA COMMUNITIES <p class="fragment">Hard Core (Academic, Industry, etc.)</p> <p class="fragment">Tool Nerds</p> <p class="fragment">Product Developers</p> <p class="fragment">Hackers</p> <p class="fragment">Game Emulators</p> <p class="fragment">Historical FPGA Hackers</p>